1. Field of the Invention
The present invention relates to a data supplying apparatus for supplying instructions (instruction codes) and/or data to be processed to an instruction executing unit and, in particular, to a data supplying apparatus with a reduced structure and a simple controlling process for supplying data to the instruction executing unit.
2. Description of the Related Art
Computer systems have an instruction supplying apparatus and a data supplying apparatus. The instruction supplying apparatus is composed of an instruction cache. The data supplying apparatus is composed of a data cache. A CPU (central processing unit) pre-fetches instructions and data from these caches. To practically use the instruction supplying apparatus and the data supplying apparatus, they should be of simple structure.
FIG. 1A is a block diagram showing a structure of a conventional instruction supplying apparatus.
Referring to FIG. 1A, the conventional instruction supplying apparatus comprises a cache data unit 1, a cache tag unit 2, an instruction buffer 3, a cache controlling unit 4, and an instruction buffer controlling unit 5. The cache data unit 1 stores instructions. When the CPU supplies an address to the cache data unit, it outputs an instruction corresponding to an index included in the address. The cache tag unit 2 stores a tag. When the CPU supplies an address to the cache tag unit 2, it outputs a tag corresponding to an index included in the tag. The cache tag unit 2 determines whether the output tag hits or misses the tag included in the address and outputs the result. The instruction buffer 3 queues an instruction received from the cache data unit 1 and sends it to an instruction executing unit. The cache controlling unit 4 controls the cache data unit 1 and the cache tag unit 2. The instruction buffer controlling unit 5 controls the instruction buffer 3.
The instruction buffer 3 normally has 10 to 20 entries for queuing instructions. A large instruction buffer may have 54 entries.
The cache controlling unit 4 receives a hit/mis-hit signal from the cache tag unit 3, generates valid information that represents whether or not an instruction in the cache data unit 1 is valid, and outputs the valid information to the instruction buffer controlling unit 5. The instruction buffer controlling unit 5 sends information that represents whether or not the next entry to be input into the instruction buffer 3 exists to the cache controlling unit 4. The cache controlling unit 4 controls data output from the cache data unit 1 based on the information.
When a cache miss takes place, the cache controlling unit 4 stores an identification (ID) of a miss instruction and compares the ID thereof with an ID of an instruction received from an external storing unit. When these IDs match, the cache controlling unit 4 stores the move-in data at a relevant entry position in the cache data unit 1. In addition, the cache controlling unit 4 informs this situation in which the move-in data is hit to the instruction buffer controlling unit 5.
Thus, the instruction buffer controlling unit 5 stores the move-in data to the relevant entry position in the instruction buffer 3. Consequently, the move-in data is stored in the cache data unit 1. In addition, the move-in data is stored in the instruction buffer 3 through the cache data unit 1 and output to the instruction executing unit.
In the conventional instruction supplying apparatus, when the instruction executing unit does not issue an instruction release signal, instructions read from the cache data unit 1 are queued in the instruction buffer 3. When the instruction executing unit issues the instruction release signal, the instructions are successively read from the instruction buffer 3 and sent to the instruction executing unit.
FIG. 1B is a timing chart showing the instruction supplying process. In FIG. 1B, the instruction buffer 3 has two stages 0 and 1.
When the instruction executing unit issues an instruction supply request, in cycle T1 of FIG. 1B, a cache access address is sent to the cache data unit 1 and the cache tag unit 2.
Thereafter, in cycle T2, the cache data unit 1 and the cache tag unit 2 are accessed. Thus, it is determined whether or not instructions read from the cache data unit 1 accord with required instructions. The instructions read from the cache data unit 1 are sent to the instruction buffer 3.
When instructions are sent from the cache data unit 1 to the instruction buffer 3 in cycle T2 and the instruction executing unit issues the instruction release signal, the instructions are read from the instruction buffer 3 and sent to the instruction executing unit in cycle T3. When the instruction release signal is not issued, the instructions are stored in the stages 0 and 1 of the instruction buffer 3 as represented after cycle T6. When the instruction release signal is issued again, the instructions queued are successively read and sent to the instruction executing unit as represented after cycle T8.
In the conventional instruction supplying apparatus, the cache data unit 1 and the instruction buffer 3 individually store instructions.
However, recently, so as to increase the data processing speed, a cache unit that is different from the conventional external cache unit is disposed in the same CPU chip.
In other words, as shown in FIG. 1C, along with a conventional cache unit (secondary cache unit) 6B disposed between a CPU chip 6C and a main storing unit 6A, new cache units 7A and 7B that function as primary cache units are disposed in the same CPU chip 6C.
When the primary cache units 7A and 7B are used, the primary instruction cache unit 7B which stores the instructions and an instruction buffer unit 7C that stores instructions that are read from the primary instruction cache unit 7B, are disposed in the same chip. The primary instruction cache unit 7B comprises the cache data unit 1, the cache tag unit 2, and the cache controlling unit 4 shown in FIG. 1A. The instruction buffer unit 7C includes the instruction buffer 3 and the instruction buffer controlling unit 5. The instruction pipeline 7D accords with the instruction executing unit. Thus, the cache data unit 1 and the instruction buffer 3 redundantly store instructions. Consequently, the resources are wastefully used.
Particularly, in a computer system using instructions of long length, the instruction buffer 3 requires a large storage capacity. Thus, this problem is significant.
However, in the conventional instruction supplying apparatus, signals should be complicatedly exchanged between the cache controlling unit 4 and the instruction buffer controlling unit 5 so as to perform the instruction buffer control and move-in control.
Normally, the primary instruction cache unit 7B and the instruction buffer unit 7C are designed by different designers. Thus, when the signals exchanged between these units are complicated, this adversely affect the designs of the units, thereby increasing the designing time.
In FIG. 1C, when a data buffer unit that stores data for calculations required by the instruction pipeline 7D is disposed between the primary data cache unit 7A and the instruction pipeline 7D, the same problem as described above with the instruction buffer unit 7C and the primary instruction cache unit 7B takes place.